This invention relates to a latch type level shift circuit and more particularly to a latch type level shift circuit used for a row decode circuit.
Recently, a flash EEPROM has received much attention as a nonvolatile semiconductor memory which can be integrated with high integration density. The memory has a feature that data items of memory cells can be instantaneously erased in a lump in the unit of block.
As the flash EEPROM, a NOR type, NAND type and the like are known. In any type of flash EEPROM, the cell structure may be generally formed of a stack type by stacking a plurality of polysilicon layers to form a floating gate electrode and control gate electrode.
FIG. 1 shows the main portion of a NOR type flash EEPROM as an example of the flash EEPROM.
A memory cell array 11 has a plurality of memory cells MC arranged in an array form. For example, the memory cell MC has a stack type cell structure as shown in FIG. 2. A plurality of word lines WL0, WL1, . . . , WLn extending in the row direction and a plurality of bit lines BL0, BL1, . . . , BLm extending in the column direction are arranged on the memory cell array 11.
For example, a plurality of row decode circuits RD.cndot.0, R.cndot.1, . . . , RD.cndot.n are respectively provided for the plurality of word lines WL0, WL1, . . . , WLn. One end of the word line WLi (i is 0, 1, . . . , n) is connected to the corresponding row decode circuit RD.cndot.i.
A column selecting circuit 12 is connected to the plurality of bit lines BL0, BL1, . . . , BLm and selects one of the columns based on an output signal from a column decode circuit CD. The bit line on the selected column is electrically connected to an input register 13 or sense amplifier 14. An input/output buffer 15 is provided to transfer data between the interior and the exterior of the memory chip.
A row address signal is input to the plurality of row decode circuits RD.cndot.0, RD.cndot.1, . . . , RD.cndot.n via an address register 16. A column address signal is input to the column decode circuit CD via the address register 16.
FIG. 3 shows one example of the row decode circuit and a control circuit therefore.
The row decode circuit RD.cndot.i is constructed by a row decoder 29 and latch type level shift circuit 30.
The row address signal is input to the row decoder 29 via the address register 16. The row decoder 29 supplies decode signals Ai, Ai indicating the result of decoding of the row address signal to the latch type level shift circuit 30. When the row containing the word line WLi is selected, the decode signal Ai is set to "H" and the decode signal Ai is set to "L".
A write enable signal WE, chip enable signal CE and command signal are input to a mode select circuit 23. The mode select circuit 23 supplies erase signals ERASE*, ERASE* to the latch type level shift circuit 30.
A potential generating circuit (booster or charge pump circuit) 24 outputs VROW (positive potential or ground potential). VROW is supplied to the latch type level shift circuit 30 via a regulator 25. A potential generating circuit (booster or charge pump circuit) 26 outputs VBB (ground potential or negative potential). VBB is supplied to the latch type level shift circuit 30 via a regulator 27.
A negative potential detecting circuit 28 detects the value of VBB, sets VBBDET to "H" when VBB is lower than a preset value (for example, -4V) and sets VBBDET to "L" when VBB is higher than the preset value. Further, it sets VBBDET to the same value as VBB when VBB is set at a negative potential and sets VBBDET to "H" when VBB is set at a ground potential.
FIG. 4 shows one example of the row decoder.
The row decoder includes a NAND circuit 17 supplied with a row address signal and an inverter circuit 18. The NAND circuit 17 outputs a decode signal Ai and the inverter circuit 18 outputs a decode signal Ai.
FIG. 5 shows one example of the latch type level shift circuit 30.
A latch circuit constructed by inverter circuits INV1, INV2 is connected between nodes A and B. The node B is connected to the input terminal of an inverter circuit INV4. An output signal OUT of the inverter circuit INV4 is supplied to the word line WLi. A signal VBBDET is input to an inverter circuit INV3 and an internal power supply potential VROW' is output from the inverter circuit INV3. The internal power supply potentials VROW', VBB are supplied to the inverter circuits INV1, INV2, INV4.
N-channel MOS transistors MN1, MN3 are serially connected between the node A and a ground node VSS and N-channel MOS transistors MN2, MN4 are serially connected between the node B and the ground node VSS. The gates of the MOS transistors MN3, MN4 are supplied with a signal VBBDET.
The signal VBBDET is set to the same value as VBB when VBB is set at a negative potential and is set to "H" when VBB is set at the ground potential.
The gate of the MOS transistor MN1 is supplied with an output signal VAB of a NOR circuit 21 and the gate of the MOS transistor MN2 is supplied with a signal VA obtained by inverting the output signal VAB of the NOR circuit 21 by use of an inverter circuit 22. Output signals of AND circuits 19, 20 are input to the NOR circuit 21. The AND circuit 19 is supplied with the decode signal Ai and erase signal ERASE* and the AND circuit 20 is supplied with the decode signal Ai and erase signal ERASE*.
In the flash EEPROM with the above construction, generally, the selected word line is applied with a positive or negative high potential. For example, at the time of program (the operation for injecting electrons into the floating gate electrode), a potential of approx. 9V is applied to the selected word line, and at the time of erase (the operation for extracting electrons from the floating gate electrode), a potential of approx. -9V is applied to the selected word line. In this case, 0V is applied to the non-selected word lines.
In the present example, the level shift circuit is formed as a latch type. Further, in order to prevent positive and negative high potentials from being simultaneously applied to the inverter circuit, the power supply potential applied to the inverter circuit is changed.
For example, when VROW' is output to the selected word line, VROW' (for example, 9V) and VBB (for example, 0V) are applied to the inverter circuit, and when VBB is applied to the selected word line, VROW' (for example, 0V) and VBB (for example, -9V) are applied to the inverter circuit.
Next, the operation of the flash EEPROM of FIGS. 1 to 5 is explained.
Program Operation (Pre-Program Operation)
First, ERASE* is set to "L", ERASE* is set to "H", VROW is set to 9V and VBB is set to 0V. Since VBB is set at 0V, the negative potential detecting circuit outputs VBBDET of "L".
Since all of the row address signals are set at "H" in the row decoder RD.cndot.i of the selected row, Ai is set to "H" and Ai is set to "L". At this time, the output signal VAB of the NOR circuit 21 is set to "L" and the output signal VA of the inverter circuit 22 is set to "H". As a result, the MOS transistor MN1 is set into the OFF state and the MOS transistor MN2 is set into the ON state.
Since VBBDET is set at "H", the MOS transistors MN3, MN4 are set in the ON state. Therefore, the ground potential Vss is transmitted to the node B of the latch circuit. That is, a potential VLB of the node B of the latch circuit is set to VBB or "L (=0V)", a potential VLA of the node A is set to VROW' or "H (=9V)", and the state of the latch circuit is determined. Since the potential VLB of the node B is set at "L", the output signal OUT of the inverter circuit INV4 is set to "H (=9V)".
When VBBDET is set at "L", the internal power supply potential VROW' (=VROW=9V) is supplied to the inverter circuits INV1, INV2, INV4. Therefore, the output signals of the inverter circuits INV1, INV4 are set to "H (=9V)".
Then, the output signal OUT (=9V) of the inverter circuit INV4 is applied to the selected word line WLi and if the potential is maintained for a preset period of time, the program operation (pre-program operation) for injecting electrons into the floating gate electrode is effected.
For example, the above program operation is repeatedly effected according to the sequence of FIG. 7 until the program operation for all of the memory cells is completed.
In the normal program operation, a "0" program operation (the operation for injecting electrons into the floating gate electrode) and a "1" program operation (the operation for maintaining the erase state) are provided. The pre-program operation is to equalize the threshold voltages of the memory cells prior to the erase operation in order to prevent over erase and corresponds to the "0" program operation.
Since all of the row address signals are not set at "H" in the row decoder RD.cndot.i of the non-selected row, Ai is set to "L" and Ai is set to "H". At this time, the output signal VAB of the NOR circuit 21 is set to "H" and the output signal VA of the inverter circuit 22 is set to "L". As a result, the MOS transistor MN1 is set into the ON state and the MOS transistor MN2 is set into the OFF state.
Since VBBDET is set at "H", the MOS transistors MN3, MN4 are set in the ON state. Therefore, the ground potential Vss is transmitted to the node A of the latch circuit. That is, the potential VLA of the node A of the latch circuit is set to VBB or "L (=0V)", the potential VLB of the node B is set to VROW' or "H (=9V)", and the state of the latch circuit is determined. Since the potential of the node B is set at "H", the output signal OUT of the inverter circuit INV4 is set to "L (=0V)". The output signal OUT is applied to the non-selected word lines.
In the program operation, a voltage of VROW'-VBB=9V is applied to the inverter circuits INV1, INV2, INV4.
Erase Operation
The erase operation is explained with reference to the signal waveforms of FIG. 6.
First, in the initial state (period (1)), ERASE* is set at "H", ERASE* is set at "L", VROW is set at 4V and VBB is set at 0V. Since VBB is set at 0V, the negative potential detecting circuit 28 outputs VBBDET="L (0V)".
Since all of the row address signals are set at "H" in the row decoder of the selected row, Ai is set at "H" and Ai is set at "L". At this time, the output signal VAB of the NOR circuit 21 is set to "H" and the output signal VA of the inverter circuit 22 is set to "L". As a result, the MOS transistor MN1 is set into the ON state and the MOS transistor MN2 is set into the OFF state.
Since VBBDET is set at "H", the MOS transistors MN3, MN4 are set in the ON state. Therefore, the ground potential Vss is transmitted to the node A of the latch circuit. That is, the potential VLA of the node A of the latch circuit is set to VBB or "L (=0V)", the potential VLB of the node B is set to VROW' or "H (=4V)", and the state of the latch circuit is determined. Since the potential of the node B is set at "H", the output signal OUT of the inverter circuit INV4 is set to "L (=0V)".
Since all of the row address signals are not set at "H" in the row decoder of the non-selected row, Ai is set to "L" and Ai is set to "H". At this time, the output signal VAB of the NOR circuit 21 is set to "L" and the output signal VA of the inverter circuit 22 is set to "H". As a result, the MOS transistor MN1 is set into the OFF state and the MOS transistor MN2 is set into the ON state.
Since VBBDET is set at "H", the MOS transistors MN3, MN4 are set in the ON state. Therefore, the ground potential 0V (VSS) is transmitted to the node B of the latch circuit. That is, the potential VLB of the node B of the latch circuit is set to VBB or "L (=0V)", the potential VLA of the node A is set to VROW' or "H (=4V)", and the state of the latch circuit is determined. Since the potential of the node B is set at "L", the output signal OUT of the inverter circuit INV4 is set to "H (=4V)".
After this, if ERASE is changed from "L" to "H", the potential generating circuit (booster or charge pump circuit) 26 gradually lowers VBB from 0V towards -9V (period (2)).
At this time, if the MOS transistors MN3, MN4 are kept in the ON state, the ground node VSS and the VBB terminal of the inverter circuit INV1 are short-circuited via the MOS transistor MN3 and node A in the selected row and the ground node VSS and the VBB terminal of the inverter circuit INV2 are short-circuited via the MOS transistor MN4 and node B in the non-selected row, thereby causing a leak current to flow.
If VBB is set at a negative potential, the negative potential detecting circuit 28 changes VBBDET from "H" (4V) to VBB. VBBDET is an inverted signal of VBBDET, but in a period in which VBB is set at a negative potential, VBBDET is changed to VBB irrespective of VBBDET.
Further, if VBBDET is set equal to VBB, the above leak current can be eliminated since the MOS transistors MN3, MN4 are always kept in the cut-off state.
In a period (3), that is, when VBB becomes lower than -4V, the negative potential detecting circuit 28 outputs VBBDET ="H". At this time, VROW (=VROW') is changed from 4V to 0V. In other words, the "H" level of each of the inverter circuits INV1, INV2, INV4 is set to 0V and the "L" level is set to VBB.
After this, if VBB reaches -9V, a negative high potential (-9V) is applied to the selected word line. If the potential is kept applied to the selected word line for a preset period of time, electrons in the floating gate electrode of the selected memory cell are discharged into the substrate or source.
At the time of erase operation, the maximum voltage applied to the inverter circuits INV1, INV2, INV4 is set to VROW' (0V)-VBB (-9V) =9V. The voltage is the same as the maximum voltage applied to the inverter circuits INV1, INV2, INV4 at the time of program operation.
If ERASE is set to "L", the erase operation is terminated and the potential generating circuit (booster or charge pump circuit) 26 tends to return VBB from -9V to the ground potential (0V). At the same time, VBBDET changes in the same manner as VBB.
In a period (4), that is, when VBB exceeds -4V, the negative potential detecting circuit 28 changes VBBDET from "H" to "L". At this time, VROW (=VROW') is returned to 4V from 0V.
When VBB is set to 0V (period (5)), the negative potential detecting circuit 28 returns VBBDET to VROW (=4V). The state in the period (5) is the same as the initial state (the state in the period 1)), and the above erase operation is repeatedly effected according to the sequence of FIG. 7, for example, until the erase operation for all of the memory cells is completed.
The conventional latch type level shift circuit described above has the following defects.
First, the following defect associated with prevention of the leak current at the time of generation of the negative potential is given.
The negative potential detecting circuit supplies VBB to the gate electrodes of the N-channel MOS transistors MN3, MN4 used as the transfer gates when VBB is set at the negative potential. As a result, even if VBB is set to a negative potential, the MOS transistors MN3, MN4 are cut off and a leak current can be prevented from flowing.
However, in this case, in order to prevent the leak current flow, it is necessary to control the ON/OFF states of the MOS transistors MN3, MN4 by logically effecting the control operation for setting VBBDET to "H (=4V)" when VBB is set at 0V and setting VBBDET to the same value as VBB when VBB is set at a negative potential.
Therefore, the conventional latch type level shift circuit has a defect that the negative potential detecting circuit becomes complicated in construction and the circuit scale thereof becomes large.
Second, the following defect associated with the read operation (verify operation) is given.
In the flash EEPROM, for example, the erase verify operation for verifying whether data of the memory cell is correctly erased or not is effected after the erase operation. At the time of verify read, for example, as shown in FIG. 8, a read potential Vread is applied to the control gate electrode of a memory cell selected to be verified and a ground potential (0V) is applied as a read inhibition potential to the control gate electrodes of non-selected memory cells.
At this time, the relation between the state ("0" or "1") of the memory cell and the threshold voltage Vth as shown in FIG. 9 is obtained and the non-selected memory cell is set in the OFF state in principle. Therefore, whether data of the selected memory cell is correctly erased or not (whether it is set to the "1" state or not) can be easily determined by detecting whether the selected memory cell is set into the ON state or kept in the OFF state.
However, for example, the erase characteristics (the ease with which data can be erased) of the memory cells are different for each memory cell according to process fluctuations in the control gate electrodes and floating gate electrodes in the manufacturing process as shown in FIG. 10. Therefore, a memory cell having a good erase characteristic will be set into an over erase state (the threshold voltage becomes negative) in some cases after data items of all of the memory cells are erased.
In this case, as shown in FIG. 11, if the non-selected memory cell in the over erase state is connected to the same bit line as the bit line BLi to which the selected memory cell is connected, the non-selected memory cell is set into the ON state, thereby discharging the precharge potential of the bit line BLi. Therefore, the bit line potential is discharged irrespective of the state in which data of the selected memory cell is correctly erased or not and the result of verify indicating that the erase operation is completed is always attained.
In order to prevent this phenomenon, for example, a potential (for example, -2V) lower than 0V may be applied to the non-selected word line so as to prevent the memory cell set in the over erase state and connected to the same bit line as that to which the selected memory cell is connected from being set into the ON state. With this, for example, at the time of verify read, the memory cell in the over erase state can be prevented from being set into the ON state.
However, the operation for applying the negative potential (for example, -2V) to the non-selected word line at the time of verify operation requires the following control operation.
(1) An address is set and latched (time tset).
(2) The VBB terminal of the inverter circuit is disconnected from the ground node and a negative potential (-2V) generated from the negative potential generating circuit is applied to the VBB terminal (time tiso).
(3) Verify read is performed (time tev).
(4) The VBB terminal of the inverter circuit is connected to the ground node (time tiso).
(5) The state of (1) is restored (time tset).
The above-described verify operation has a feature that the operations of (2) and (4) are newly added in comparison with the normal verify operation. The operations of (1) to (5) are based on substantially the same sequence as the erase operation.
Since the erase operation is effected collectively and simultaneous for all of the memory cells, the erase sequence is effected by one time when data erase is effected for all of the memory cells by one time. However, the verify operation is effected for each memory cell. Therefore, when the verify operation is effected for all of the memory cells by one time, the above sequence is effected by the number of times equal to the number of rows (the number of word lines).
For example, in a case where 1024 rows are present in one memory cell array (or block) and if verify read is effected for all of the memory cells by one time, the total time becomes 1024.times.(2.times.tset+2.times.tiso+tev).
Thus, in order to prevent a leak current from flowing due to an over erase cell at the read time (at the verify time), the control operation by the sequence of (1) to (5) described above is required, thereby causing a problem that the operation control becomes complicated and the verify time becomes excessively long.